)]}'
{
  "commit": "71396cd048072b69559b46d98cfebfd4474cd712",
  "tree": "3b29b3ce3f469473600816c6fdabf79e858ce91b",
  "parents": [
    "79704a88eb5aa70fa506e3e59a29fcda21f428af"
  ],
  "author": {
    "name": "fangming.fang",
    "email": "fangming.fang@arm.com",
    "time": "Fri Dec 24 08:29:04 2021 +0000"
  },
  "committer": {
    "name": "Tomas Mraz",
    "email": "tomas@openssl.org",
    "time": "Fri Jan 14 11:40:05 2022 +0100"
  },
  "message": "SM3 acceleration with SM3 hardware instruction on aarch64\n\nSM3 hardware instruction is optional feature of crypto extension for\naarch64. This implementation accelerates SM3 via SM3 instructions. For\nthe platform not supporting SM3 instruction, the original C\nimplementation still works. Thanks to AliBaba for testing and reporting\nthe following perf numbers for Yitian710:\n\nBenchmark on T-Head Yitian-710 2.75GHz:\n\nBefore:\ntype  16 bytes     64 bytes    256 bytes    1024 bytes   8192 bytes   16384 bytes\nsm3   49297.82k   121062.63k   223106.05k   283371.52k   307574.10k   309400.92k\n\nAfter (33% - 74% faster):\ntype  16 bytes     64 bytes    256 bytes    1024 bytes   8192 bytes   16384 bytes\nsm3   65640.01k   179121.79k   359854.59k   481448.96k   534055.59k   538274.47k\n\nReviewed-by: Paul Dale \u003cpauli@openssl.org\u003e\nReviewed-by: Tomas Mraz \u003ctomas@openssl.org\u003e\n(Merged from https://github.com/openssl/openssl/pull/17454)\n",
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